1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for controlling a multi-chamber processing tool.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes include the initial growth of the semiconductor material, the slicing of the semiconductor crystal ingot into individual wafers, the fabrication stages (etching, doping, ion implanting, and the like), and the packaging and final testing of the completed device.
As technology advances facilitate smaller critical dimensions for semiconductor devices, the need for reduction of errors increases dramatically. Proper formation of sub-sections within a semiconductor device is an important factor in ensuring proper performance of the manufactured semiconductor device. Critical dimensions of the sub-sections generally have to be within a predetermined acceptable margin of error for semiconductor devices to be within acceptable manufacturing quality and performance ranges.
Certain types of tools used to process semiconductor wafers include multiple processing chambers and paths. The tools, commonly referred to as multi-chamber processing tools, are operated using a plurality of operating recipes. The operating recipes may vary between chambers of different types and even among chambers of the same type. Wafers are loaded into one end of the processing tool and progress through the tool as the various processing steps are performed. One exemplary multi-chamber tool is a tool that performs an etch process in one chamber and a photoresist stripping process in another chamber. Typically, the tool has multiple etch chambers and multiple strip chambers. The path through the tool may vary. For example, the wafers processed in one of the etch chambers may not necessarily progress to the same strip chamber for the next processing step. During the setup of the tool, the operating recipes of the chambers are configured to handle a range incoming wafer characteristics (e.g., photoresist layer thickness). The variations inherent in the incoming wafers, as well as the variations introduced by proceeding through different paths through the processing tool, result in corresponding variations in the outgoing product.
For example, because of variations in the incoming photoresist layer thicknesses, the strip process includes a predetermined amount of overstrip time (i.e., strip time in excess of the time required to remove a photoresist layer with average thickness). Accurate control of the stripping process is important for preventing defects in the wafer. If the photoresist strip time is too short (i.e., understripping), remnants of the photoresist layer will be present on the wafer, interfering with subsequent processing steps. If the strip time is too long (i.e., overstripping), the wafer may be damaged by unnecessary exposure to ion charging effects, and also the processing time for completing the wafer is lengthened. Typically, a minimum strip time designed to provide a certain amount of overstripping to ensure complete removal of the photoresist is programmed into the recipe of the developer. However, variations in the photoresist, developer, photoresist layer thickness, etc., may result in different photoresist strip rates for various wafers in the same or different lots. Accordingly, a minimum strip time does not always ensure that all of the photoresist is removed. Raising the strip time to encompass such process variations could result in wafer damage and lengthen processing time.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.